1. Field of the Invention
The present invention relates to the field of displaying technology, and in particular to a method for manufacturing an active matrix organic light-emitting diode (AMOLED) backplane.
2. The Related Arts
In the field of displaying technology, flat panel display technology, such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), has gradually taken the place of cathode ray tube (CRT) displays, and among them, the OLEDs have various advantages, such as being self-luminous, low driving voltage, high light emission efficiency, short response time, high clarity and contrast, virtually 180° view angle, wide temperature range of applications, being capable of flexible displaying, and full color displaying in a large area, and are considered a display device with the best potential of development.
The OLEDs can be classified, according to the type of driving, as passive OLEDs (such as passive matrix OLEDs (PMOLEDs)) and active OLEDs (such as active matrix OLEDs (AMOLEDs)). The AMOLEDs are generally a self-luminous device composed of a low-temperature polysilicon (LTPS) driving backplane and an electroluminescent layer. LTPS has high electron mobility. For AMOLED, using the material of LTPS has various advantages including high resolution, high response speed, high brightness, high aperture ratio, and low power consumption.
A structure of a commonly used AMOLED backplane in the prior art techniques is illustrated in FIG. 1. The manufacturing process of the AMOLDED backplane is generally as follows:
Step 1: depositing a buffer layer 200 on a substrate 100;
Step 2: depositing an amorphous (a-Si) layer on the buffer layer 200 and applying laser treatment to crystalize and convert the amorphous silicon layer into a polysilicon layer; and then applying photolithographic and etching processes to subject the polysilicon layer to patterning treatment so as to form a first polysilicon section 301, a second polysilicon section 303, and a third polysilicon section 305 that are arranged to be spaced from each other;
Step 3: depositing a gate insulation layer 400;
Step 4: applying a photolithographic process to form a first photoresist pattern on the gate insulation layer 400;
Step 5: with the first photoresist pattern as a shielding layer, subjecting the patternized polysilicon layer to P-type heavy doping so as to form P-type heavy-doping areas P+ on opposite sides of the second polysilicon section 303 and the third polysilicon section 305;
Step 6: first removing the first photoresist pattern and then applying a photolithographic process to form a second photoresist pattern on the gate insulation layer;
Step 7: with the second photoresist pattern as a shielding layer, subjecting the patternized polysilicon layer to N-type heavy doping to form N-type heavy-doping areas N+ on opposite sides of the first polysilicon section 301;
Step 8: removing the second photoresist pattern and depositing and patterning a first metal layer on the gate insulation layer 400 to form a first gate terminal 601, a second gate terminal 605, and an electrode plate 603;
Step 9: with the patternized first metal layer as a shielding layer, subjecting the patternized polysilicon layer to ion implanting (self-align) to form light-doping drain areas N− on opposite sides of the first polysilicon section 301.
Step 10: sequentially forming an interlayer insulation layer 700, first and second source/drain terminals 810, 830, a planarization layer 900, an anode 1000, a pixel definition layer 1100, and photo spacers 1200 on the gate insulation layer 400.
The first source/drain terminals 810 are electrically connected to the N-type heavy-doping areas N+ of the first polysilicon section 301 and the second source/drain terminals 830 are electrically connected to the P-type heavy-doping areas P+ of the second polysilicon section 303; and the anode 1000 is electrically connected to the second source/drain terminals 830.
The first polysilicon section 301, the first gate terminal 601, and the first source/drain terminals 810 collectively form a switching TFT; the second polysilicon section 303, the second gate terminal 603, and the second source/drain terminals 830 collectively form a driving TFT; and the third polysilicon section 305 and the electrode plate 605 collectively form a storage capacitor
An AMOLED backplane manufactured with the above-described method suffers certain problems. If the photolithographic process of Step 6 that is conducted before N-type heavy doping is shifted, it is easy to make the light-doping drain areas that are located on opposite sides of a channel area of switching TFT not symmetric.